The present invention relates to a current limiting circuit for limiting the current flow through a power FET, such as a MOSFET or similar insulated gate transistor. In particular, the circuit prevents a potentially damaging current flowing through the power transistor in a short circuit or other over current condition.
Many electrical circuits comprising a power transistor driving a load include a current limiting circuit to limit the current drawn through the transistor, particularly in a short circuit condition, to prevent damage to the power transistor and/or load. One form of current limiting circuit widely used in bipolar transistor circuits is a current mirror. A current mirror essentially sinks a pre-determined current through a control transistor which limits the current through a power transistor to a multiple of the sink current in proportion to the ratio of the structural sizes of the two xe2x80x98mirrorxe2x80x99 transistors. A power transistor may be a mirror transistor which is coupled to the output of the main drive transistor, or the main drive transistor may itself be the mirror transistor directly controlled by the control transistor.
Current mirrors have also been implemented to provide short circuit current protection for insulated gate transistors such as MOSFETs, although a different approach must be taken to that applied to bipolar transistors given the difference in structure. An example of a current limiting circuit for MOSFETs based on a current mirror configuration is described in U.S. Pat. No. 4,612,497. In this prior art circuit a current mirror comprising a pair of current mirror transistors, and a sink current transistor, are used to control the current through a drive transistor. The current mirror pair comprises a first control transistor and a much larger power transistor which is connected in series between the drive transistor and the output. The gates of the mirror transistors are coupled together so that the current flowing through the larger mirror transistor is controlled as a proportion of a sink current flowing through the control transistor and sink transistor. A disadvantage of this circuit is that the control transistor is always conducting and thus drawing power. This problem is addressed by U.S. Pat. No. 6,285,177.
U.S. Pat. No. 6,285,177 describes a current limiting circuit for a MOSFET in which a control transistor is only switched into conduction, to conduct an appropriate sink current, when a short circuit condition is detected. In this circuit the gate of the drive transistor is coupled to the gate of the control circuit so as to form one of the pair of current mirror transistors. The control transistor, which is much smaller than the power drive transistor, is coupled to an appropriate current source. A switching transistor is coupled in series between the control transistor and the output of the drive transistor (which is configured as a source follower). For normal operating conditions the switching transistor, and thus the control transistor, are non-conducting. However, in a short circuit condition the voltage at the output of the drive transistor, and thus switch transistor drops to zero (or near zero) which activities the switch transistor. The switch transistor in turn activates the control transistor into a conducting state. The predetermined sink current then flows through the control transistor with the result that the current drawn through the drive transistor is limited by the structural ratio of the control and drive transistors to a predetermined multiple of the sink current.
U.S. Pat. No. 6,285,177 further describes a semi-conductor device structure in which the switch transistor and drive transistor can be integrated on the same device. The device has a cellular configuration and a minor portion of the drain cells are available for use either as drain cells of the main drive transistor or of the smaller switch transistor. The exact apportionment of cells is achieved by providing appropriately configured separate drain contact layers for the main drive transistor and the switch transistor.
A disadvantage of the above circuit is that it can only be implemented in a horizontal device, i.e. a device in which the drain and source regions are provided in the same (upper) surface of the device substrate. The circuit cannot be implemented in a more space efficient vertical structure in which the drain is provided on the opposite side of the substrate to the source regions and gate contacts. Furthermore, this prior art circuit can only be applied to a drive transistor operating in a high side application (e.g. configured as a source follower) whereas vertical MOSFETs are often used in low side applications (e.g. an N MOSFET with the output taken from the drain).
It is an object of the present invention to obviate or mitigate the above disadvantages.
According to a first aspect of the present invention there is provided a a current-limit circuit comprising:
a power transistor;
a control transistor coupled to the power transistor in a current mirror configuration and powered from the gate of the power transistor;
and switching circuitry operatively coupled between the output of the power transistor and the control transistor to selectively activate the control transistor in response to an over current condition, whereby current drawn through the power transistor in the over current condition is limited by the control transistor.
An advantage of the first aspect of the present invention is that no separate power supply is necessary for the control transistor of the current mirror since this derives its power directly from the gate signal supplied to the power transistor.
According to a second aspect of the present invention there is provided a current limit circuit comprising:
a power transistor;
a control transistor coupled to the power transistor in a current mirror configuration;
a switch transistor coupled in series with the control transistor; and
a detect transistor operatively coupled between the power transistor and the switch transistor to activate the switch transistor in an over current condition detected at the output of the power transistor.
An advantage of the second aspect of the present invention is that the separate detect transistor provides a convenient means of connecting the switch transistor to the control transistor which is particularly useful when implementing the circuit in a vertical semi-conductor structure as described further below. Another advantage of the second aspect of the present invention in that the detect transistor provides a means of limiting the voltage passed to the switch transistor to prevent damage to the switch transistor in an over current condition.
The term xe2x80x9cover current conditionxe2x80x9d refers to any condition in which the current rises above an acceptable level for normal operation of the device. A typical over current condition will be a short circuit condition but the invention is not limited to short circuit protection. For instance, the invention can be applied to limit the inrush current when driving inductive loads such as lamps, motors, car ignition coils etc. Other possible applications of the invention will be apparent to the skilled person.
According to a third aspect of the present invention there is provided a semi-conductor device having first and second insulated gate transistors integrated on a semi-conductor substrate of a first conductivity type defining first and second surfaces, comprising:
an array of adjacent transistor body regions of a second conductivity type provided adjacent said first surface;
gate electrodes extending between adjacent body regions and insulated therefrom by a gate insulator layer;
transistor source regions of said first conductivity type provided in said body regions adjacent said gate electrodes;
transistor source electrode material overlying the gate electrodes and insulated therefrom by an intervening insulation layer, said source electrode material contacting said source/body regions between adjacent gate electrodes;
wherein the source electrode layer is patterned to define first and second adjacent regions providing source contact to the first and second transistors respectively; and
gate electrodes of the first transistor are isolated from adjacent gate electrodes of the second transistor by intervening body regions devoid of source regions adjacent one or both of said adjacent gate electrodes.
The structure according to the third aspect of the present invention enables integration of a power transistor and detect transistor on a single substrate whilst isolating the source and gate contacts of one transistor from the other. Furthermore, the structure allows the device to be implemented in an efficient planar or trench vertical structure.